自作MCPサーバー その8 #AI - Qiita
@ohisama@github

Building a Custom MCP Server, Part 8

  • Custom MCP
  • AI
  • ClaudeDesktop
  • DesktopCommander
  • Verilog
0
Posted at 2026-11-11
TAG40@@

Overview

I became interested in MCP servers, so I looked into them.
I asked the AI.
I tried using Desktop-Commander.
I tried simulating Verilog.

Do you know Verilog?

Yes, I do. Verilog is a hardware description language (HDL) for describing digital circuits and is used in FPGA design as well as ASIC design and verification. It can also handle SystemVerilog (an extension of Verilog with enhanced verification features).

What It Can Do

  • Describing combinational and sequential circuits (adders, counters, state machines, FIFOs, etc.)
  • Creating testbenches (clock generation, input stimulus, and verification with $display and $monitor)
  • Writing code for waveform (VCD) output
  • Reviewing existing code, fixing bugs, and rewriting it in a synthesisable form
  • Consultation on coding style (how to use blocking and nonblocking assignments, avoiding unintended latch inference, etc.)

About Simulation
To simulate Verilog, you need tools such as Icarus Verilog (iverilog / vvp) or Verilator. GTKWave is commonly used to view waveforms. Whether these are installed on your PC can be checked in the same way as csc a moment ago. If they are, I can write the code in C:\Users\ohisa\claude and run the simulation together with you.

Shall I check?

//set PATH=C:\iverilog\bin;%PATH%

//set PATH=C:\iverilog\gtkwave\bin;%PATH%

So iverilog is in C:\iverilog\bin and GTKWave is in C:\iverilog\gtkwave\bin. Let me confirm that they actually exist.

All three—iverilog, vvp, and gtkwave—were found. The version is Icarus Verilog 12.0 (devel).

Command Path
iverilog C:\iverilog\bin\iverilog.exe
vvp C:\iverilog\bin\vvp.exe
gtkwave C:\iverilog\gtkwave\bin\gtkwave.exe

The `set PATH=...` line you posted is written for cmd (batch files), but I use PowerShell, so I wrote the equivalent as `$env:PATH = "C:\iverilog\bin;C:\iverilog\gtkwave\bin;" + $env:PATH`, and it works. This PATH setting is valid only within that command. Therefore, when I run it, I prepend this line every time or invoke it using the full path.

Now you can simulate Verilog. You can write a circuit (for example, a counter) and a testbench in C:\Users\ohisa\claude, then try running iverilog → vvp and outputting the VCD waveform. Since GTKWave is a GUI application, launching it opens a window on the screen.

What kind of circuit would you like to try? If you haven’t decided, shall we verify its operation with a 4-bit counter?

Please

The 4-bit counter simulation ran successfully.

Files created (C:\Users\ohisa\claude)

  • counter4.v: A 4-bit counter with synchronous reset and enable
  • counter4_tb.v: Testbench (using a 10 ns clock, it performs reset, count, stop, and reset again, in that order)
  • counter4.vcd: Waveform data

Points to check in the results

  • The initial count=x indicates that the value was indeterminate before reset. It was reset to 0 on the first clock cycle.
  • While en=1, the value increased from 0 to 15 and then returned to 0 (because it is 4 bits, it overflowed and wrapped around once).
  • Setting en=0 holds the value (count=2). Then, setting rst=1 returned it to 0.
  • The time is displayed as t=5000 because the output is in units of ps. 5000 represents 5 ns.

Would you like to view the waveform in GTKWave? When it is launched, a window will open on your screen.

Please

GTKWave has been launched (process ID 5396). A window should now be open on your screen.The window title is the path to the executable, and since `counter4.vcd` is not shown in it, I cannot confirm whether the waveform file was loaded.

How to display the waveform

  1. In the SST pane in the upper left, click `counter4_tb`.
  2. Select `clk`, `rst`, `en`, and `count[3:0]` from the signal list below.
  3. Use Append (or double-click a signal) to add them to the waveform pane on the right.
  4. If the waveform is too small, use Time → Zoom Fit (or Ctrl+Alt+F) in the menu to display the entire waveform.

For `count[3:0]`, right-click and select Data Format → Decimal to change it to decimal display, which makes it easier to read.

Please let me know if the window does not open or the signals do not appear.

Photo

image.png

counter4.v

// 4-bit counter (with synchronous reset and enable) module counter4 ( input wire clk, input wire rst, // Synchronous reset (cleared when High) input wire en, // Count enable output reg [3:0] count ); always @(posedge clk) begin if (rst) count <= 4'd0; else if (en) count <= count + 4'd1; end endmodule

counter4_tb.v

`timescale 1ns/1ps module counter4_tb; reg clk = 0; reg rst = 1; reg en = 0; wire [3:0] count; counter4 dut (.clk(clk), .rst(rst), .en(en), .count(count)); // Clock with a 10 ns period always #5 clk = ~clk; // Waveform output initial begin $dumpfile("counter4.vcd"); $dumpvars(0, counter4_tb); end // Display results initial $monitor("t=%0t rst=%b en=%b count=%0d", $time, rst, en, count); // Input stimulus initial begin #12 rst = 0; // Release reset #8 en = 1; // Start counting #180 en = 0; // Count for 18 clock cycles and stop (wraps around once because it is 4 bits) #20 rst = 1; // Reset #20 rst = 0; #20 $finish; end endmodule

End.